1. Field of the Invention
The present invention relates to an integrated chip package structure and method of manufacture the same. More particularly, the present invention relates to an integrated chip package structure and method of manufacture the same using silicon substrate.
2. Description of related art
In the recent years, the development of advanced technology is on the cutting edge. As a result, high-technology electronics manufacturing industries launch more feature-packed and humanized electronic products. These new products that hit the showroom are lighter, thinner, and smaller in design. In the manufacturing of these electronic products, the key device has to be the integrated circuit (IC) chip inside any electronic product.
The operability, performance, and life of an IC chip are greatly affected by its circuit design, wafer manufacturing, and chip packaging. For this present invention, the focus will be on chip packaging technique. Since the features and speed of IC chips are increasing rapidly, the need for increasing the conductivity of the circuitry is necessary so that the signal delay and attenuation of the dies to the external circuitry are reduced. A chip package that allows good thermal dissipation and protection of the IC chips with a small overall dimension of the package is also necessary for higher performance chips. These are the goals to be achieved in chip packaging.
There are a vast variety of existing chip package techniques such as ball grid array (BGA), wire bonding, flip chip, etc. . . . for mounting a die on a substrate via the bonding points on both the die and the substrate. The inner traces helps to fan out the bonding points on the bottom of the substrate. The solder balls are separately planted on the bonding points for acting as an interface for the die to electrically connect to the external circuitry. Similarly, pin grid array (PGA) is very much like BGA, which replaces the balls with pins on the substrate and PGA also acts an interface for the die to electrically connect to the external circuitry.
Both BGA and PGA packages require wiring or flip chip for mounting the die on the substrate. The inner traces in the substrate fan out the bonding points on the substrate and electrical connection to the external circuitry is carried out by the solder balls or pins on the bonding points. As a result, this method fails to reduce the distance of the signal transmission path but in fact increase the signal path distance. This will increase signal delay and attenuation and decrease the performance of the chip.
Wafer level chip scale package (WLCSP) has an advantage of being able to print the redistribution circuit directly on the die by using the peripheral area of the die as the bonding points. It is achieved by redistributing an area array on the surface of the die, which can fully utilize the entire area of the die. The bonding points are located on the redistribution circuit by forming flip chip bumps so the bottom side of the die connects directly to the printed circuit board (PCB) with micro-spaced bonding points.
Although WLCSP can greatly reduce the signal path distance, it is still very difficult to accommodate all the bonding points on the die surface as the integration of die and internal devices gets higher. The pin count on the die increases as integration gets higher so the redistribution of pins in an area array is difficult to achieve. Even if the redistribution of pins is successful, the distance between pins will be too small to meet the pitch of a printed circuit board (PCB).